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o2611 sy pc no.a1990-1/23 specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appli ances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliab ility and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. LV23411V overview the LV23411V is single chip tuner ic, and fm/am radio is able to be realized with few external parts. functions ? fm tuner ? am tuner ? mpx stereo decoder ? tuning system features ? no alignments necessary ? reduction of external component counts ? large audio output signal is av ailable for home stereo systems ? worldwide fm band support (64 to 108mhz) ? worldwide am band support (520 to 1710khz) ? soft-mute, stereo-blend function ? lv23411 corresponds to europe immunity standard (en55020-s1) ? i 2 c control interface bi-cmos lsi for home stereo systems fm/am tuner ic orderin g numbe r : en*a1990
LV23411V no.a1990-2/23 specifications absolute maximum ratings at ta = 25 c, gnd1 = gnd2 = gnd3 = gnd4 = gnd5 = 0v parameter symbol conditions ratings unit maximum supply voltage v cc max 10.0 v digital output voltage v o max sda 3.6 v v in 1 max sda, scl 3.6 v digital input voltage v in 2 max clk in 3.6 v allowable power dissipation pd max ta 70 c *1 450 mw operating temperature topr -20 to +70 c storage temperature tstg -40 to +125 c *1 : mounted on a specified board. board size is 114.3mm 76.1mm 1.6mm, glass epoxy. operating conditions at ta = 25 c, gnd1 = gnd2 = gnd3 = gnd4 = gnd5 = 0v parameter symbol conditions ratings unit recommended supply voltage v cc 9.0 v register 1eh bit 1 (levshif) = 0 4.5 to 6.5 v operating supply voltage range * note v cc op register 1eh bit 1 (levshif) = 1 8.5 to 9.5 v * note : supply the stabilized voltage. interface conditions at ta = -20 to +70 c, gnd1 = gnd2 = gnd3 = gnd4 = gnd5 = 0v ratings parameter symbol conditions min typ max unit v ih 1 sda, scl 2.3 3.5 v high level input voltage v ih 2 clk in 2.3 3.5 v v il 1 sda, scl 0 0.5 v low level input voltage v il 2 clk in 0 0.3 v output voltage v o sda 0 3.5 v crystal frequency fin clk in 32.768 khz crystal frequency accuracy faccuracy -100 +100 ppm operating characteristics at ta = 25 c, v cc = 9.0v, with the designated circuit. ratings parameter symbol conditions min typ max unit [fm characteristics ; mono] : fc = 98mhz, v in = 60db v, fm = 1khz, de-emphasis = 50 s, if = 225khz, bw = 45% mono : 75khz dev stereo : l+r = 67.5khz dev, pilot = 7.5khz dev volume level = 3, register 1eh bit 1 (levshif) = 1, pin 9 output, audio filter = ihf-bp f, soft mute = off ,soft stereo = off current drain i cc fm no input 35 40 45 ma 30db s/n sensitivity sn30 s/n = 30db input level 10 15 db v signal-to-noise ratio snr mono 62 70 db thd mono 0.5 1.5 % total harmonic distortion thd-st stereo 0.5 2.5 % demodulation output v o 3 mono 518 775 1160 mvrms sd operation level sd fs = 4 17 25 33 db v mute attenuation mute mono 60 75 db stereo separation sep pin 10 output/pin 9 output 20 35 db carrier leak cl stereo snr, audio filter = off 30 40 db stereo on level st-on l+r = 67.5khz dev, pilot level 3.0 6.5 % [am characteristics] : fc = 1mhz, v in = 94db v, fm = 400hz, mod = 30% if = 53khz, bw = 50% volume level = 2, register 1eh bit 1 (levshif) = 1, pin 9 output, audio filter = 15khz lpf off current drain i cc am no input 30 35 40 ma 20db s/n sensitivity sn20 s/n = 20db input level 48 65 db v signal-to-noise ratio snr 42 50 db total harmonic distortion thd 0.8 2.8 % demodulation output v o 2 122 173 245 mvrms sd operation level sd fs = 4 46 54 64 db v mute attenuation mute 15khz lpf on 50 65 db
LV23411V no.a1990-3/23 package dimensions unit : mm (typ) 3259 block diagram sanyo : tssop30(275mil) 7.6 5.6 0.65 (1.0) 9.75 0.5 0.15 1 15 30 16 0.22 (0.33) 0.08 1.2max 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 fll osc cap local oscillator tuning system bpf divider agc det image det gnd ref .osc st out sd out ant cap lna ldo state machine power management demodulator de-emphasis stereo blend audio amp. stereo decoder lna
LV23411V no.a1990-4/23 pin descriptions pin pin name i/o descriptions remarks dc voltage 1 am-ant i am antenna input c onnect to pin2 through matching coil or ferrite antenna. - 2 am-ref o reference voltage for am part connect to pin1 through matching coil or ferrite antenna. 2.2v 3 am-cap i am capacitor bank exteranal indu ctor (recommendation value) is connected between this pin and gnd. - 4 gnd1 - am antenna gnd connected to gnd 0v 5 vref1 o reference voltage for analog capacitor of 1 f is connected between this pin and gnd. 4.3v 6 mpx in_out o demodulato output when rds used, lc72725 is applicable 2.5v 7 am rf-agc o am rf ag c output capacitor of 1 f is connected between this pin and gnd. - 8 gnd2 - analog gnd connected to gnd 0v 9 l-out o audio lch output 10 r-out o audio rch output according to the v cc _application, reference output_level setting is cangeable by register bit. register 1eh bit 1 (levshif) =1: register 1eh bit 1 (levshif) =0: 2.6v (3.7v) 11 v cc -low - voltage supply pi n at low voltage operation mode when using v cc < 6v, connect to pin15 directly - 12 am lcf o am low_cut filter capacitor of 0.047uf is connected between this pin and gnd. 2.2v 13 sd-out o sd indicator output active low output 3.0v (0.1v) 14 st-out o st indicator output active low output 3.0v (0.1v) 15 v cc - voltage supply pin - 16 clk_in i reference clock input 32.768khz crystal connected to gnd. it is also applicable to input directly clock signals ( square wave gnd_reference) - 17 if agc cap - if-agc m onitor point (test) open - 18 sd-adj - adjustment for sd on level incase of changing sd on level, put resistor between this pin and gnd. - 19 nc i - 20 scl i i 2 c interface clk input - 21 sda i/o i 2 c interface data input/output - 22 vref2 o output voltage pin for v dd v dd output_pin of 3.0v. this pin is applicable to supply the current other ic up to 10ma. 3.0v 23 gnd3 - digital gnd for control part 0v 24 l1 - local oscillator 39nh connected to pin 25 - 25 vref3 o reference voltage for local osc part 5.0v 26 l2 - local oscillator 39nh connected to pin 25 - 27 gnd4 - analog gnd for osc part connected to gnd 0v 28 fll-cap - oscillator tuning vo ltage output capacitor of 0.1 f is connected between this pin and gnd. - 29 gnd5 - analog gnd for fmrf part connected to gnd 0v 30 fm-ant i fm antenna input 1 input impedance is 75 0.8v
LV23411V no.a1990-5/23 pin internal circuit description pin no. pin name pin voltage (v) description internal equivalent circuit 1 am-ant 2.2 am antenna input pin. the am antenna coil is connected between pins 40 and this pin. r = 100 1 2 rr 2 am-ref 2.2 reference voltage pin for am. vam-ref = 2.2v 15 2 2.2v regulator 3 am-cap - tuning pinl for am. (am capacitor bank) 3 cap-bank 4 gnd1 0 gnd pin for analogue am_fe part. 5 vref1 4.3 analogue part (tuner) reference bias terminal. vref1 = 4.3v 15 5 4.3v regulator 6 mpx in_out 2.5 fm demodulation output /input for mpx. r = 100 r 6 7 am rf-agc - pin for am_rf agc. r1 = 2m r2 = 5k r3 = 250 r4 = 1k r4 r3 r1 r2 7 8 gnd2 0 gnd pin for analogue tuner part. 9 10 l-out r-out 2.6 (3.7v when levshif = 1) l-ch (r-ch) output pin. r = 100 r out = 150 r 9 15 10 continued on next page.
LV23411V no.a1990-6/23 continued from preceding page. pin no. pin name pin voltage (v) description internal equivalent circuit 11 v cc -low - when using with v cc < 6.0v, 11pin-15 pin is shorted. 15 11 5v regulator 4.3v regulator 12 am lcf 2.2 terminal for am low-cut filter. r1 = 250 r2 = 100k r3 = 100k r4 = 50k r5 = 50k r1 r2 r4 r5 12 r3 13 sd-out 3.0 (less than 0.1) sd indicator output pin. active low output. r = 100k 22 13 r sd sw 14 st-out 3.0 (less than 0.1) fm stereo indicator output pin active low output r = 100k 22 14 r st sw 15 v cc v cc analogue part power supply pin. when using 8.5 to 9.5v, set to register 1eh bit 1 (levshif) = 1 when using with v cc < 6.5v, set to register 1eh bit 1 (levshif) = 0 and 11pin-15pin must be shorted ? 16 clk_in 2.1 (osc mode) for internal reference clock. 32.768khz crystal connected to gnd. it is also applicable to input directly clock signals ( square wave gnd_reference) r = 100 crystal oscillator r 16 17 if agc cap - this pin is for test. open r1 = 1.5k , r2 = 1k , r3 = 500 17 r1 r2 r3 18 sd-adj - open normally. adjust pin for sd sensitivity with to k resistor connected to gnd comp r 18 continued on next page.
LV23411V no.a1990-7/23 continued from preceding page. pin no. pin name pin voltage (v) description internal equivalent circuit 19 nc - 20 scl - digital interface clk line. r = 1k r 20 scl 21 sda digital interface data line. (interactive data communication line.) require pull_up resistor 3.3k to 10k between this pin and vref2 (v dd ). r = 250 data data r 21 22 vref2 3 reference voltage output pin for logic part. vref2 = 3v 15 22 3v regulator 23 gnd3 0 gnd pin for digital part (control part). 24 26 l1 l2 5 osc coil of 39nh to be connected between this pin and pin 25. cap bank 26 24 cap bank 25 vref3 5 reference voltage pin for local oscillation circuit. 15 25 5v regulator 27 gnd4 0 gnd pin for local oscillation circuit. 28 fll-cap - lpf pi n for controlled fll internally. r = 80k 28 29 gnd5 0 gnd pin for local oscillation circuit. continued on next page.
LV23411V no.a1990-8/23 continued from preceding page. pin no. pin name pin voltage (v) description internal equivalent circuit 30 fm-ant 0.8 fm antenna input pin fm. r = 1.5k rin = 75 30 r 29 used parts component parameter value tolerance type supplier l1 local osc coil 39nh 5% ll2012-fhl39nj toko l2 local osc coil 39nh 5% ll2012-fhl39nj toko l3 am loop antenna 18.1 h 5% 4910-csl18r1jn1 sagami a90326057 coils t1 am rf matching 250 h - #7003rns-a1109yzs toko c1 ripple filter 1 f c2 am rf agc capacitor 1 f c3 coupling capacitor 1 f c4 coupling capacitor 1 f c5 supply bypass capacitor 0.1 f c6 supply bypass capacitor 22 f c7 am low-cut filter 0.1 f c8 supply bypass capacitor 22 f c9 osc filter 0.1 f c10 ripple filter 0.1 f r1 pulled-up resistor 4.7k r2 pulled-up resistor 4.7k r3 sd adjust resistor to k bpf fm ant bpf - - gfmb7 soshin x1 crystal 32.768khz 100ppm dt-26 kds lo1 am ferrite antenna 260 h tbd - -
LV23411V no.a1990-9/23 format of bus transfers bus transfers are prim arily based on the i 2 c primitives ? start condition ? repeated start condition ? stop condition ? byte write ? byte read start, restart, and stop conditions are specified as shown in table 1 below. start repeated start stop fig. 1 the i 2 c start, repeated start and stop conditions. for details, like timing, etc., refer to specifications of i 2 c. 8-bit write 8-bit data is sent from the master microcomputer to lv23411. data bit consists of msb first and lsb last. data transmission is latched at the rising edge of scl in synchronization with the scl clock generated at the master ic. do not change data while scl remains high. lv23411 outputs the ack bit between eighth and ninth falling edges of scl fig. 2 signal pattern of the i 2 c byte write read is of the same form as write, only except that the data direction is opposite. eight data bits are sent from lv23411 to the master while ack is sent from the master to lv23411. fig. 3 signal pattern of the i 2 c byte read the serial clock scl is supplied from the master side. it is essential that data bit is output from lv23411 in synchronization with the falling edge while the mast er side performs latching at the rising edge. scl sda scl sda scl sda scl sda d7 d6 d5 d4 d3 d2 d1 d0 ack scl sda d7 d6 d5 d4 d3 d2 d1 d0 ack
LV23411V no.a1990-10/23 lv23411 latches ack at the rising edge. the sequence to write data d into the register a of lv23411 is shown below. ? start condition ? write the device address (c0h) ? write the register address, a ? write the target data, d ? stop condition fig. 4 register write through i 2 c when one or more data has been provided for writing, only the first data is allowed to be written. read sequence ? start condition ? write the device address (c0h) ? write the register address, a ? repeated start condition (or stop + start in a single master network) ? write the device address + 1 (c1h) ? read the register contents d, tran smit nack (no more data to be read) ? stop condition fig. 5 register read through i 2 c interrupt pin int lv23411 has the dedicated interrupt output pin. for the active level to the host, either low or high can be selected. the int output pin is kept floating while the pwrad bit is cleared during initialization. therefore, to avoid influence on the cpu side during initia lization, it is recommended to secure the non-active state by means of the pull-up or pull-down resistor. this enables direct int output connection to non-masking interruption of the host cpu. scl sda da7 start write device address write register address stop write data byte da6...1 ack a7 a6...1 d7 d6...0 ack ack scl sda da7 start write device address rep. write register address write device address + 1 stop start read data byte with nack da6...1 ack a7 a6...0 da7 da6...1 d7 d6...0 ack ack
LV23411V no.a1990-11/23 digital interface specification (interface specification : reference) (1). characteristics of sda and scl bus line relative to the i 2 c bus interface standard-mode high_speed-mode parameter symbol min max min max unit scl clock frequency f scl 0 100 0 400 khz fall time of both sda and scl tf 300 20+0.1cb 300 ns rise time of both sda and scl tr 1000 20+0.1cb 300 ns high time of scl t high 4.0 0.6 s low time of scl t low 4.7 1.3 s hold time of stat condition t hd ; sta 4.0 0.6 s hold time of data t hd ; dat 03.45 0 0.9 s set-up time of stat condition t su ; sta 4.7 0.6 s set-up time of stop condition t su ; sto 4.0 0.6 s set-up time of data t su ; dat 250 100 ns bus free time between a stop and start condition t buf 4.7 1.3 s capacitivie load for each bus line cb 400 400 pf *cb = total capacitance of one bus line scl sda t high repeated star t t su;sta t hd;dat t su;dat t hd;sta t low tr start condition tf tf tr
LV23411V no.a1990-12/23 description of the register of LV23411V register 00h - chip_id - chip identify register (read-only) 7 6 5 4 3 2 1 0 id[7:0] bit 7-0 : id[7:0] : 8-bit chip id lv243411 : 1bh note : to abort the command, write any value in this register. register 01h - chip_rev - chip revi sion identify register (read-only) 7 6 5 4 3 2 1 0 revision[7:0] bit 7-0 : id[7:0] : 8-bit chip revision es1 : 00h note : to abort the command, write any value in this register. register 02h - radio_stat - radi o station status (read-only) 7 6 5 4 3 2 1 0 im_stat im_fs[1:0] mo_st fs[2:0] tuned bit 7 : im_stat : state of image-station avoidance 0 = normal (possible to write) 1 = the image-station avoidance is being processed (impossible to write) note : this bit works only at register14h_bit7 (im_evas) is set to ?1?. the writing processing to lv23411 is prohibited when this bit is ?1?. bit 6-5 : im_fs : image-signal fieldstrength 0 : no image-signal 1 : there are weak image-signal that level is less -10db or more weaker than desire?s 2 : the level of the image ?signal is around 0 - 10db compared with desire?s 3 : the level of the image-signal is +10db or more stronger than that of desire?s bit 4 : mo_st : mono/stereo indicator 0 = forced monaural 1 = normal (receiving in stereo mode) bit 3-1 : fs[2:0] : fieldstrength 0 : fs < 10 db v 1 : fs = 10 - 20 db v 2 : fs = 20 - 30 db v 7 : fs > 70 db v bit 0 : tuned : radio tuning flag. 0 = no tuned 1 = tuned note : when the tuning command succeeds, this bit is set. this bit is cleared unde r 3 conditions as below. 1. pw_rad = 0 2. tuning frequency 3. when fll becomes outside the correction range
LV23411V no.a1990-13/23 register 04h - tnpl - tune position low (read-only) 7 6 5 4 3 2 1 0 tunepos[7:0] bit 7-0 : tunepos[7:0] : current rf frequency (low 8 bit) register 05h - tnph_stat - tune position high/status (read-only) 7 6 5 4 3 2 1 0 error[1:0] tunepos[12:8] bit 7-6 : error[1:0] : error code error[1:0] remark 0 ok, command end (no error) 1 dac limit error 2 command forced end 3 command busy bit 5:0 : tunepos[13:8] : current rf frequency (high 5 bit) register 06h - count_l - counter low (read-only) 7 6 5 4 3 2 1 0 count[7:0] bit 7-0 : count[7:0] : counter value (low 8 bit) register 07h - count_h - counter high (read-only) 7 6 5 4 3 2 1 0 count[15:8] bit 7-0 : count[15:8] : counter value (high 8 bit) register 08h - if_osc - dac for if osc (read/write) 7 6 5 4 3 2 1 0 ifosc[7:0] bit 7-0 : ifosc[7:0] : if oscillator dac register 09h - ifbw-dac for if - filter band width (read/write) 7 6 5 4 3 2 1 0 ifbw[7:0] bit 7-0 : ifbw[7:0] : if-filter band width dac register 0bh - stereo_osc - dac for stereo decoder osc (read/write) 7 6 5 4 3 2 1 0 sdosc[7:0] bit 7-0 : sdosc[7:0] : ster eo decoder oscillator dac register 0ch - rf_osc - dac for rf osc (read/write) 7 6 5 4 3 2 1 0 rfcap[7:0] bit 7-0 : rfosc[7:0] : rf oscillator dac register 0dh - rfcap - rf cap bank (read/write) 7 6 5 4 3 2 1 0 rfcap[7:0] bit 7-0 : rfcap[7:0] : rf oscillator capacitor-bank
LV23411V no.a1990-14/23 register 0eh - amcap1 - am - ant cap bank1 (read/write) 7 6 5 4 3 2 1 0 amcap[7:0] bit 7-0 : amcap[7:0] : am antenna capacitor-bank note : the am antenna capacitor bank is composed of 12 bits. high 4 bit is arranged at ?amctrl? register. register 0fh - amctrl - am station control (read/write) 7 6 5 4 3 2 1 0 amdiv[2:0] am_cal acap11 acap10 acap9 acap8 bit 7-5 : amdiv[2:0] : am clock divider bit 7 : am_cd2 : am clock divider bit 2. bit 6 : am_cd1 : am clock divider bit 1. bit 5 : am_cd0 : am clock divider bit 0. note : the am_cd[2:0] is used to decr ease frequency from fm - band to am - band. please set am_cd to ?0? at fm mode. am_cd[2:0] divide-rate am-rf frequency (in khz) 0,1 divider off 0 (fm mode) 2 224 338 - 483 3 160 474 - 676 4 112 676 - 966 5 80 947 - 1353 6 64 1183 - 1692 7 48 1578 - 2256 bit 4 : na (fixed to ?0?) bit 3-0 : amcap[11:8] : am antenna capacitor-bank bit 3 : amcap_bit 11 bit 2 : amcap_bit 10 bit 1 : amcap_bit 9 bit 0 : amcap_bit 8 register 10h - do_ref_clk_cnf - do output mode and reference clock configuration (read/write) 7 6 5 4 3 2 1 0 ipol do_sel[1:0] ext_clk_cfg[1:0] fs_s[2:0] bit 7-5 : na (fixed to ?0?) bit 4-3 : ext_clk_cfg[1:0] : external clock setting ext_clk_cfg[1:0] reference clock 00 off 01 oscillator clock source (external clock source) 10 32768hz crystal oscillator 11 no use bit 2-0 : fs_s[2:0] : sd (station detector) operation level setting
LV23411V no.a1990-15/23 register 11h - if_sel - if frequency selection (read/write) 7 6 5 4 3 2 1 0 fll_mod amif[2:0] fmif[3:0] bit 7 : fll_mod: fll operation mode 0 : smoothing filter = off 1 : smoothing filter = on bit 6-4 : amif[2:0] : if fre quency setting at am mode amif[2:0] 0 1 2 3 4 5 6 7 20khz 31khz 42khz 53khz 64khz 75khz 86khz 97khz bit 3-0 : fmif[3:0] : if frequency setting at fm mode (khz) fmif[3:0] se_am rf_sel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 112.5 125 137.5 150 162.5 175 187.5 212.5 225 237.5 250 262.5 275 287.5 312.5 325 0 1 112.5 127.5 142.5 157.5 157.5 172.5 187.5 202.5 217.5 232.5 247.5 262.5 277.5 292.5 307.5 322.5 register 12h - ref_clk_mod - slope correction (read/write) 7 6 5 4 3 2 1 0 refmod[7:0] bit 7-0 : refmod[7:0] : reference clock collection
LV23411V no.a1990-16/23 register 13h - sm_ctrl - statemachine control (read/write) 7 6 5 4 3 2 1 0 fll_on clks_se[2:0] nsd_pm nif_pm cm_se[1:0] bit 7 : fll_on : fll control 0 = fll off 1 = fll on bit 6-4 : clks_se : cl ock source selection 0 = no select 1 = stereo decoder oscillator is selected 2 = if oscillator is selected 3 = am antenna oscillator is selected 4 = fm rf oscillator is selected 5 = am rf oscillator is selected 6 - 7 = no select note : bit[6-4] set oscillator source. select arbitrary clock oscillator at tuning or calibrations or measure. bit 3 : nsd_pm : stereo decoder pll mute 0 = sd pll off (calibration) 1 = sd pll on (normal operation) bit 2 : nif_pm : if pll mute 0 = if pll off (calibration) 1 = if pll on (normal operation) bit 1-0 : cm_se : command mode selection 0 = no command 1 = measure mode 2 = calibration mode 3 = radio tuning (rf frequency tuning) mode note : this bit used to select command mode. select the arbitrary command to be executed. the command is executed by setting target_val_l/h. command execution time : sd calibration = 540ms if calibration = 134ms rf (fm) tuning = 105ms rf (am) tuning = 158ms note: please wait the time provided for the above-mentioned befo re all processing including reading the register after having executed the command.
LV23411V no.a1990-17/23 register 14h - ref_clk_prs - reference clock pre-scaler (read/write) 7 6 5 4 3 2 1 0 im_evas reserved wait_sel am_fine refpre[3:0] bit 7 : im_evas : image signal avoidance function on/off 0 = off 1 = on (recommend) bit 6 : reserved : fixed to ?0? bit 5 : wait_sel : selection mute release standby time after tuning 0 = 8ms wait 1 = 4ms wait bit 4 : am_fine : selection am_ant adjustment standby time 0 = no wait when dac value is changed 1 = 2ms wait when dac value is changed bit 3-0 : refpre[3:0] : reference clock pre- scaler 0 = 1 : 1 1 = 1 : 2 2 = 1 : 4 15 = 1 : 32768 register 15h - ref_clk_div - reference clock divider (read/write) 7 6 5 4 3 2 1 0 refdiv[7:0] bit 7-0 : refdiv[7:0] : reference clock divider 0 : divide rate = 1 1 : divide rate = 2 255 : divide rate = 256 register 16h - target_val_l - target value low register (read/write) 7 6 5 4 3 2 1 0 target[7:0] bit 7-0 : target[7:0] : target frequency low 8 bit : tuning frequency or calibration frequency : low byte register 17h - target_val_h - target value high register (read/write) 7 6 5 4 3 2 1 0 target[15:8] bit 7-0 : target[15:8] : target frequency high 8 bit : tuning frequency or calibration frequency : high byte with radio power on, lower eight bits of the target frequency are set. then, set higher eight bits of the target frequency to t his register. the command is executed. tunepos and target : - am mode : 1khz span - fm mode : 10khz span
LV23411V no.a1990-18/23 register 18h - radio_ctrl1 - radio control 1 (read/write) 7 6 5 4 3 2 1 0 iqc_ctr ifpol osc_lev[1:0] deem vol[1:0] en_amhc bit 7 : iqc_ctr : i/q phase change 0 = normal mode (upper heterodyne) 1 = i/q phase change : for image signal avoidance (lower heterodyne) note : usually, no-need to change bit 6 : if pole change by state machine 0 = the if frequency is added to local frequency (normal) 1 = the if frequency is subtracted from local frequency note : usually, no-need to change bit 5-4 : osc_lev[1:0] : rf-o sc oscillation level setting 0 = minimum level 3 = maximum level note : 3db steps, le vel = 2 is recommended bit 3 : deem : de-emphasis setting 0 = 50 s : korea china, europe, japan 1 = 75 s : usa bit 2-1 : vol[1:0] : volume setting 0 = minimum (vol0) 3 = maximum (vol3) bit 0 : en_amhc : am high-cut filter on/off 0 = am hcf off 1 = am hcf on register 19h - radio_ctrl2 - radio control 2 (read/write) 7 6 5 4 3 2 1 0 reserved reserved en_amm reserved if_agc_lev rf_agc_lev[1:0] en_rfagc bit 7 : reserved : fixed to ?0? bit 6 : reserved : fixed to ?1? bit 5 : en_amm : am mute on/off 0 = am mute off 1 = am mute on bit 4 : reserved : fixed to ?0? bit 3 : if_agc_lev : if-agc level control 0 = agc slow mode 1 = agc first mode bit 2-1 : rf_agc_lev[1:0] : rf-agc level control 0 = agc slow mode 1 = agc normal mode 3 = agc first mode bit 0 : en_rfagc : rf-agc on/off 0 = agc off 1 = agc on (normal)
LV23411V no.a1990-19/23 register 1ah - radio_ctrl3 - radio control 3 (read/write) 7 6 5 4 3 2 1 0 deem_100 na if_agc_cap am_wid e_agc_off am_wide_agc_on bit 7 : deem_100 : additional de-emphasis (100 s) 0 = 0 s (default setting) 1 = 100 s (deem = 1 : 75 s) bit 6 : na bit 4 : if_agc_cap 0 = off (normal) 1 = on bit 3-2 : am_wide_agc_off[1:0] : am wide agc off level control 0 = first mode 3 = slow mode bit 1-0 : am_wide_agc_on[1:0] : am wide agc on level control 0 = wide agc off 1 = first mode 3 = slow mode register 1ch - stereo_ctrl1 - stereo control 1 (read/write) 7 6 5 4 3 2 1 0 crc[1:0] ss_sp2 reserved reserved pican_en fostereo st_m bit 7-6 : crc[1:0] : capture range control 0 = narrow mode 3 = wide mode bit 5 : ss_sp2 : stereo=on sensitivity speed2 (first mode) 0 : first mode = off 1 : first mode = on (recommend) bit 4 : reserved : fixed to ?0? bit 3 : reserved : fixed to ?0 bit 2 : pican_en : pilot signal cancellation on/of 0 = off 1 = on (recommend) bit 1 : fostereo : forced stereo 0 = off (normal) 1 = on bit 0 : st_m : mono/stereo setting 0 = stereo on (normal) 1 = stereo off (forced mono)
LV23411V no.a1990-20/23 register 1dh - stereo_ctrl2 - stereo control 2 (read/write) 7 6 5 4 3 2 1 0 na foamagc reserved over_mod cpaj[2:0] bit 7-5 : na bit 4 : foamagc 0 : forced - agc = off 1 : forced - agc = on bit 3 : reserved: fixed to ?0? bit 2 : over_mod : over-modulation detector on/off 0 = off 1 = on bit 1-0 : cpaj[1:0] : channel separation adjacent 0 = minimum sub-signal level 7 = maximum sub-signal level register 1eh - radio_ctrl4 - radio control 4 (read/write) 7 6 5 4 3 2 1 0 softst[2:0] softmu[2:0] levshif fo_softt bit 7-5 : softst[2:0] : soft st ereo function (s tereo-blend) 0 : soft stereo = off 7 : soft stereo = lev7 (max) bit 4-2 : softmu[2:0] : soft audio mute function 0 : soft mute = off 7 : soft mute = lev7 (max) bit 1 : levshif : audio line-out dc level shift 0 = normal dc level (v cc = 5.0v) 1 = dc level is shifted (v cc =9.0v) bit 0 : fo_softst : forced soft stereo function 0 : on (normal) 1 : off
LV23411V no.a1990-21/23 register 1fh - radio_ctrl5 - radio control 5 (read/write) 7 6 5 4 3 2 1 0 rf_sel ifrim nagc_spd se_fm/am amp_ctr mute am_cal pw_rad bit 7 : rf_sel : rf tuning range select 0 = normal ( japan/usa/europe) 1 = oilt (65mhz to 74mhz) bit 6 : ifrim : if osc limit setting 0 : max = 350khz (fm mode) 1 : max = 150khz (am mode) bit 5 : nagc_spd : if agc speed setting 0 = high speed (fm mode) 1 = normal (am mode) bit 4 : se_fm/am : am/fm mode select 0 = fm mode 1 = am mode bit 3 : amp_ctr : audio amp on/off 0 = off 1 = on bit 2 : mute : audio mute on/off 0 = on 1 = off bit 1 : am_cal : am calibration (antenna tuning mode) 0 = am receiving mode (normal) 1 = am calibration mode (am antenna tuning mode) note : set this bit to ?1?, if ant calibration frequency is measured. bit 0 : pw_rad: radio power 0 = power off (power save mode) 1 = power on *1 : after the v cc voltage is impressed, pw_rad is automatically set to "0" in 50ms. *2 : when the v cc voltage is dropped once, content of regi sters other than pw_rad becomes irregular.
LV23411V ps no.a1990-22/23 test circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LV23411V bpf dummy ant am ant fm ant am ref gnd5 am cap fll cap gnd1 gnd4 vref1(4.3v) l2 mpx in_out vref3 (4.3v) am agc l1 gnd2 gnd3 l out vref2(3v) r out sda v cc _low scl am_lcf nc sd out nc st out if agc cap v cc clk in i 2 c_bus c10 0.1 f 50 50 50 50 c1 0.1 f c2 1 f c3 1 f mpx in_out t1 gnd lout rout sd st v cc =5v(9v) v cc =5v:short v cc =9v:open c4 1 f c5 1 f c6 0.047 f c7 0.1 f c8 22 f c9 22 f r2 4.7k r3 open x1 32.768hz r1 4.7k l1 39nh l2 39nh
LV23411V ps no.a1990-23/23 application circuit example 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LV23411V bpf am ant fm ant am ref gnd5 am cap fll cap gnd1 gnd4 vref1(4.3v) l2 mpx in_out vref3 (4.3v) am agc l1 gnd2 gnd3 l out vref2(3v) r out sda v cc _low scl am_lcf nc sd out sd adj st out if agc cap v cc clk in i 2 c_bus c10 0.1 f c1 0.1 f c2 1 f c3 1 f mpx in_out for am loop antenna t1 l3 for am ferrite antenna lo1 am cap am ref am ant gnd gnd lout rout sd st v cc =5v(9v) v cc =5v:short v cc =9v:open c4 1 f c5 1 f c6 0.047 f c7 0.1 f c8 22 f c9 22 f r2 4.7k r3 open x1 32.768hz r1 4.7k l1 39nh l2 39nh sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliab ility pr oducts, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these pr obab ilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of october, 2011. specificati ons and information herein are subject to change without notice.

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